Dual, High-Voltage Scan Driver for TFT
GOFF Rapid Discharge Function (DISH Input)
The DISH input controls a switch between GOFF and
AGND. When DISH is pulled below ground by at least
1V, VGOFF is rapidly discharged to AGND. Typically
DISH is capacitively coupled to VDD so that if VDD falls
suddenly, VGOFF is quickly discharged to AGND.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the device. When
the junction temperature exceeds TJ = +160°C, a thermal sensor immediately shuts down the scan driver outputs. The outputs are set to high impedance. Once the
device cools down by approximately 15°C, the device
reactivates.
The thermal-overload protection protects the IC in the
event of overheat conditions. For continuous operation,
do not exceed the absolute maximum junction temperature rating of TJ = +150°C.
Applications Information
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environment and the ambient temperature. The thermal resistance depends on the IC package, PCB copper area,
other thermal mass, and airflow.
The MAX17109, with its exposed backside pad soldered
to 1in2 of PCB copper, can dissipate about 34.5mW into
+70°C still air. More PCB copper, cooler ambient air, and
more airflow increase the possible dissipation, while
less copper or warmer air decreases the IC’s dissipation capability.
Scan Driver Outputs
The power dissipated by the scan driver outputs (CKV1,
CKVB1, STVP1, CKV2, CKVB2, and STVP2) depends on
the scan frequency, the capacitive load, and the difference between the GON and GOFF supply voltages:
where fSCAN is the scan frequency of the panel, CPANEL
is the panel model capacitive load, VGON and VGOFF
are the positive gate-on and negative gate-off voltages.
If both scan drivers operate at a frequency of fSCAN =
50kHz, the load of the six outputs is CPANEL = 5nF, and
the supply voltage difference is VGON - VGOFF = 30V,
then the power dissipated is 1.35W.
PCB Layout and Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
1) Place the GON, GOFF, and VDD pin bypass capacitors as close as possible to the device. The ground
connections of the GON, GOFF, and VDD bypass
capacitors should be connected directly to the
AGND pin with a wide trace.
2) Avoid using vias in the high-current paths. If vias
are unavoidable, use many vias in parallel to reduce
resistance and inductance.
3) Connect the MAX17109’s exposed paddle to AGND
copper plane and the copper plane area should be
maximized to improve thermal dissipation.
4) Minimize the length and maximize the width of the
traces between the CKV, CKVB, and STV output nodes
and the panel load for best transient responses.
Refer to the MAX17109 evaluation kit for an example of proper board.
Dual, High-Voltage Scan Driver for TFT LCD
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High-Voltage Level-Shifting Scan Driver
The MAX17109 includes two, 3-channel, high-voltage,
level-shifting scan drivers. The scan driver outputs
(CKV1, CKV2, CKVB1, CKVB2, STVP1, and STVP2)
swing between the power-supply rails (VGON and
VGOFF) according to their corresponding input logic
levels. The states of the CKV1, CKVB1, and STVP1 outputs are determined by the input logic levels present on
OE, OECON, STV1, and CPV1. The states of the CKV2,
CKVB2, and STVP2 outputs are determined by the input
logic levels present on OE, OECON, STV2, and CPV2
(See Figure 3, Tables 1 and 2.)
STV1 and STV2 are the vertical timing signals. CPV1
and CPV2 are the horizontal timing signals. OE is the
output-enable signal. OECON is a timing signal derived
through an RC filter from OE that blanks OE if OE stays
high for too long. These signals have CMOS input logic
levels set by the VDD supply voltage. CKV1 and CKV2
are scan clock outputs, which are complementary to
scan clock outputs CKVB1 and CKVB2, respectively.
STVP1 and STVP2 are the output scan start signals.
These output signals swing from VGON to VGOFF, which
have a maximum upper level of +40V, a minimum lower
level of -30V, and a combined maximum range of VGON
- VGOFF = 65V. Their low output impedance enables
them to swiftly drive capacitive loads. The input pins
CKVCS1, CKVBSC1, CKVBCS2, and CKVBCS2 allow
the charge in the panel equivalent capacitors to be
shared. This reduces the power loss in state transition.
General Description
The MAX17109 includes two high-voltage, level-shifting
scan drivers for TFT panel integrated gate logic. Each
scan driver has 2 channels that switch complementarily. The scan driver outputs swing from +40V to
-30V and can swiftly drive capacitive loads. To save
power, the scan driver’s complementary outputs share
the charge of their capacitive load before they change
states.
The MAX17109 is available in a 32-pin, 5mm x 5mm,
thin QFN package with a maximum thickness of 0.8mm
for ultra-thin LCD panels.
Applications
Notebook Computer Displays
LCD Monitor and TV Panels
Features
♦ +40V to -30V Output Swing Range
♦ Fast Slew Rate for High Capacitive Load
♦ Load Charge Sharing for Power Saving
♦ 32-Pin, 5mm x 5mm, Thin QFN Package
